4.4 General Principles of Pipelining

• A key feature of pipelining is that it increases the throughput of the system (i.e., the number of customers served per unit time), but it may also slightly increase the latency (i.e., the time required to service an individual customer)

ex) 단위시간당 손님들의 수가 늘어나는 반면 손님 한명당 서비스해주는데 필요한 시간은 늘어난다.

 

4.4.1 Computational Pipelines

• Combinational logic : It consists of some logic that performs a computation, followed by a register to hold the results of this computation. 

• Clock : A clock signal controls the loading of the register at some regular time interval.

• The total time required to perform a single instruction from beginning to end is known as the latency

 

4.4.2 A Detailed Look at Pipeline Operation

• The signals propagate to the pipeline register inputs, but no change in the register states will occur until the clock rises.
• On the other hand, we could have disastrous effects if the clock were run too fast.
• The values would not have time to propagate through the combinational logic, and so the register inputs would not yet be valid when the clock rises.

 

4.4.3 Limitations of Pipelining

Nonuniform Partitioning

 

•  arithmetic and logical unit, ALU :  덧셈, 뺄셈 같은 두 숫자의 산술연산과 배타적 논리합, 논리곱, 논리합 같은 논리연산을 계산하는 디지털 회로이다. 산술 논리 장치는 컴퓨터 중앙처리장치의 기본 설계 블록이다